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DS8024 smart card interface ________________________________________________________________ maxim integrated products 1 rev 1; 8/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the DS8024 smart card interface ic is a low-cost, analog front-end for a smart card reader, designed for all iso 7816, emv*, and gsm11-11 applications. the DS8024 is a pin-for-pin drop-in replacement for the nxp tda8024 and is offered in 28-pin tssop and so packages. applications requiring support for 1.8v smart cards or requiring low power should consider the ds8113, which achieves lower active- and stop-mode power with mini- mal changes to application hardware and software. applications set-top box conditional access access control banking applications pos terminals debit/credit payment terminals pin pads automated teller machines telecommunications pay/premium television features ? analog interface and level shifting for ic card communication ? 8kv (min) esd (iec) protection on card interfaces ? internal ic card supply-voltage generation: 5.0v ?%, 80ma (max) 3.0v ?%, 65ma (max) ? automatic card activation and deactivation controlled by dedicated internal sequencer ? i/o lines from host directly level shifted for smart card communication ? flexible card clock generation, supporting external crystal frequency divided by 1, 2, 4, or 8 ? high-current, short-circuit and high-temperature protection ordering information note: contact the factory for availability of other variants and package options. + denotes a lead-free/rohs-compliant package. *emv is a trademark owned by emvco llc. emv level 1 library and hardware reference design available. contact factory for detail s. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of a ny device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . part temp range pin-package DS8024-rjx+ -40 c to +85 c 28 tssop DS8024-rrx+ -40 c to +85 c 28 so selector guide appears at end of data sheet. pgnd 28 27 26 25 24 23 22 aux2in aux1in i/oin xtal2 top view DS8024 xtal1 off gnd 21 v dd 20 rstin 19 cmdvcc 18 n.c. 17 v cc 16 rst 15 clk 5v/3v clkdiv2 clkdiv1 cp1 v dda v up pres pres i/o aux2 aux1 4 1 2 3 5 6 7 8 9 10 11 12 13 14 cgnd cp2 so/tssop pin configuration
DS8024 smart card interface 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd relative to gnd ...............-0.5v to +6.5v voltage range on v dda relative to pgnd ...........-0.5v to +6.5v voltage range on cp1, cp2, and v up relative to pgnd...............................................-0.5v to +7.5v voltage range on all other pins relative to gnd......................................-0.5v to (v dd + 0.5v) maximum junction temperature .....................................+125? maximum power dissipation (t a = -25? to +85?) .......700mw storage temperature range .............................-55? to +150? soldering temperature.........refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units power supply digital supply voltage v dd 2.7 6.0 v v cc = 5v, | i cc | < 80ma 4.0 6.0 card voltage-generator supply voltage v dda v cc = 5v, | i cc | < 30ma 3.0 6.0 v v th2 threshold voltage (falling) 2.30 2.45 2.60 v reset voltage thresholds v hys2 hysteresis 50 100 150 mv current consumption active v dd current 5v cards (including 80ma draw from 5v card) i dd_50v i cc = 80ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v 215 ma active v dd current 5v cards (current consumed by DS8024 only) i dd_ic i cc = 80ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v (note 2) 135 ma active v dd current 3v cards (including 65ma draw from 3v card) i dd_30v i cc = 65ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v 100 ma active v dd current 3v cards (current consumed by DS8024 only) i dd_ic i cc = 65ma, f xtal = 20mhz, f clk = 10mhz, v dda = 5.0v (note 2) 35 ma inactive-mode current i dd card inactive 500 a clock source crystal frequency f xtal external crystal 0 20 mhz f xtal1 0 20 mhz v il_xtal1 low-level input on xtal1 (note 3) -0.3 0.3 x v dd xtal1 operating conditions v ih_xtal1 high-level input on xtal1 (note 3) 0.7 x v dd v dd + 0.3 v external capacitance for crystal c xtal1 , c xtal2 (note 3) 15 pf internal oscillator f int 2.7 mhz shutdown temperature shutdown temperature t sd (note 3) +150 c
DS8024 smart card interface _______________________________________________________________________________________ 3 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units rst pin output low voltage v ol_rst1 i ol_rst = 1ma 0 0.3 v card-inactive mode output current i ol_rst1 v o_lrst = 0v 0 -1 ma output low voltage v ol_rst2 i ol_rst = 200a 0 0.3 v output high voltage v oh_rst2 i oh_rst = -200a v cc - 0.5 v cc v rise time t r_rst c l = 30pf (note 3) 0.1 s fall time t f_rst c l = 30pf (note 3) 0.1 s shutdown current threshold i rst(sd) -20 ma current limitation i rst(limit) -20 +20 ma card-active mode rstin to rst delay t d(rstin-rst) 2 s clk pin output low voltage v ol_clk1 i olclk = 1ma 0 0.3 v card-inactive mode output current i ol_clk1 v olclk = 0v 0 -1 ma output low voltage v ol_clk2 i olclk = 200a 0 0.3 v output high voltage v oh_clk2 i ohclk = -200a v cc - 0.5 v cc v rise time t r_clk c l = 30pf (note 3) 8 ns fall time t f_clk c l = 30pf (note 3) 8 ns current limitation i clk(limit) -70 +70 ma clock frequency f clk operational (note 3) 0 10 mhz duty factor c l = 30pf (note 3) 45 55 % card-active mode slew rate sr c l = 30pf (note 3) 0.2 v/ns v cc pin output low voltage v cc1 i cc = 1ma 0 0.3 v card-inactive mode output current i cc1 v cc = 0v 0 -1 ma i cc(5v) < 80ma 4.75 5.00 5.25 i cc(3v) < 65ma 2.78 3.00 3.22 5v card: current pulses of 40nc with i < 200ma, t < 400ns, f < 20mhz (note 3) 4.6 5.4 output low voltage v cc2 3v card: current pulses of 24nc with i < 200ma, t < 400ns, f < 20mhz (note 3) 2.75 3.25 v v cc(5v) = 0 to 5v -80 output current i cc2 v cc(3v) = 0 to 3v -65 ma shutdown current threshold i cc(sd) 120 ma card-active mode slew rate v ccsr up/down, c < 300nf 0.05 0.16 0.22 v/s
DS8024 smart card interface 4 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units data lines (i/o and i/oin) i/o i/oin falling edge delay t d(io-ioin) (note 3) 200 ns pullup pulse active time t pu (note 3) 100 ns maximum frequency f iomax 1 mhz input capacitance c i (note 3) 10 pf i/o, aux1, aux2 pins output low voltage v ol_io1 i ol_io = 1ma 0 0.3 v output current i ol_io1 v ol_io = 0v 0 -1 ma card-inactive mode internal pullup resistor r pu_io to v cc 9 11 19 k output low voltage v ol_io2 i ol_io = 1ma 0 0.3 v output high voltage v oh_io2 i oh_io = < -40a (3v/5v) 0.75 x v cc v cc v output rise/fall time t ot c l = 30pf (note 3) 0.1 s input low voltage v il_io -0.3 +0.8 input high voltage v ih_io 1.5 v cc v input low current i il_io v il_io = 0v 700 a input high current i ih_io v ih_io = v cc 20 a input rise/fall time t it (note 3) 1.2 s current limitation i io(limit) c l = 30pf -15 +15 ma card-active mode current when pullup active i pu c l = 80pf, v oh = 0.9 x v dd (note 3) -1 ma i/oin, aux1in, aux2in pins output low voltage v ol i ol = 1ma 0 0.3 v output high voltage v oh i oh < -40a 0.75 x v dd v dd + 0.1 v output rise/fall time t ot c l = 30pf, 10% to 90% (note 3) 0.1 s input low voltage v il -0.3 0.3 x v dd v input high voltage v ih 0.7 x v dd v dd + 0.3 v input low current i il_io v il = 0v 600 a input high current i ih_io v ih = v dd 10 a input rise/fall time t it v il to v ih (note 3) 1.2 s integrated pullup resistor r pu pullup to v dd 9 11 13 k current when pullup active i pu c l = 30pf, v oh = 0.9 x v dd (note 3) -1 ma
DS8024 smart card interface _______________________________________________________________________________________ 5 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units control pins (clkdiv1, clkdiv2, cmdvcc , rstin, 5v/ 3v ) input low voltage v il -0.3 0.3 x v dd v input high voltage v ih 0.7 x v dd v dd + 0.3 v input low current i il_io 0 < v il < v dd 5 a input high current i ih_io 0 < v ih < v dd 5 a integrated pullup resistor r pu pullup to v dd , 5v/ 3v only 50 85 120 k interrupt output pin ( off ) output low voltage v ol i ol = 2ma 0 0.3 v output high voltage v oh i oh = -15a 0.75 x v dd v integrated pullup resistor r pu pullup to v dd 12 20 28 k pres, pres pins input low voltage v il_pres 0.3 x v dd v input high voltage v ih_pres 0.7 x v dd v input low current i il_pres v il_pres = 0v 40 a input high current i ih_pres v ih_pres = v dd 40 a timing activation time t act 160 s deactivation time t deact 80 s window start t 3 95 clk to card start time window end t 5 160 s pres/ pres debounce time t debounce 8 ms note 1: operation guaranteed at t a = -40? and t a = +85?, but not tested. note 2: idd_ic measures the amount of current used by the DS8024 to provide the smart card current minus the load. note 3: guaranteed by design, but not production tested.
DS8024 smart card interface 6 _______________________________________________________________________________________ pin description pin name function 1, 2 clkdiv1, clkdiv2 clock divider. determines the divided-down input clock frequency (presented at xtal1 or from a crystal at xtal1 and xtal2) on the clk output pin. dividers of 1, 2, 4, and 8 are available. 3 5v/ 3v 5v/3v selection pin. allows selection of 5v or 3v for communication with an ic card. logic-high selects 5v operation; logic-low selects 3v operation. see table 3 for a complete description of choosing card voltages. 4 pgnd analog ground 5, 7 cp2, cp1 step-up converter contact. charge-pump capacitor. connect a 100nf capacitor (esr < 100m ) between cp1 and cp2. 6 v dda charge-pump supply. must be equal to or higher than v dd . connect a supply of at least 3.3v. 8 v up charge-pump output. connect a 100nf capacitor (esr < 100m ) between v up and gnd. 9 pres card presence indicator. active-low card presence inputs. when the presence indicator becomes active, a debounce timeout begins. after 8ms (typ) the off signal becomes active. 10 pres card presence indicator. active-high card presence inputs. when the presence indicator becomes active, a debounce timeout begins. after 8ms (typ) the off signal becomes active. 11 i/o smart card data-line output. card data communication line, contact c7. 12, 13 aux2, aux1 smart card auxiliary line (c4, c8) output. data line connected to card reader contacts c4 (aux1) and c8 (aux2). 14 cgnd smart card ground 15 clk smart card clock. card clock, contact c3. 16 rst smart card reset. card reset output from contact c2. 17 v cc smart card supply voltage. decouple to cgnd (card ground) with 2 x 100nf or 100 + 220nf capacitors (esr < 100m ). 18 n.c. no connection. unused on the DS8024. 19 cmdvcc activation sequence initiate. active-low input from host. 20 rstin card reset input. reset input from the host. 21 v dd supply voltage 22 gnd digital ground 23 off status output. active-low interrupt output to the host. use a 20k integrated pullup resistor to v dd . 24, 25 xtal1, xtal2 crystal/clock input. connect an input from an external clock to xtal1 or connect a crystal across xtal1 and xtal2. for the low idle-mode current variant, an external clock must be driven on xtal1. 26 i/oin i/o input. host-to-interface chip data i/o line. 27, 28 aux1in, aux2in c4/c8 input. host-to-interface i/o line for auxiliary connections to c4 and c8.
DS8024 smart card interface _______________________________________________________________________________________ 7 detailed description the DS8024 is an analog front-end for communicating with 3v and 5v smart cards. using an integrated charge pump, the DS8024 can operate from a single input voltage. the device translates all communication lines to the correct voltage level and provides power for smart card operation. it can operate from a wide input voltage range (3.3v to 6.0v). the DS8024 is compatible with the nxp tda8024 and is provided in the same packages. (note that the poradj pin is not present in the DS8024. most applications do not make use of this input pin, instead using the DS8024? default reset threshold.) power supply the DS8024 can operate from a single supply or a dual supply. the supply pins for the device are v dd , gnd, v dda , and pgnd. v dd should be in the range of 2.7v to 6.0v, and is the supply for signals that interface with the host controller. it should, therefore, be the same supply as used by the host controller. all smart card contacts remain inactive during power on or power off. the internal circuits are kept in the reset state until v dd reaches v th2 + v hys2 and for the duration of the inter- nal power-on reset pulse, t w . a deactivation sequence is executed when v dd falls below v th2 . an internal charge pump and regulator generate the 3v or 5v card supply voltage (v cc ). the charge pump and regulator are supplied by v dda and pgnd. v dda should be connected to a minimum 3.3v (maximum 6.0v) supply and should be at a potential that is equal to or higher than v dd . the charge pump operates in a 1x (voltage follower) or 2x (voltage doubler) mode depending on the input v dda and the selected card voltage (5v or 3v). for 5v cards, the DS8024 operates in a 1x mode for v dda > 5.8v and in a 2x mode for v dda < 5.8v. for 3v cards, the DS8024 operates in a 1x mode for v dda > 4.1v and in a 2x mode for v dda < 4.0v. voltage supervisor the voltage supervisor monitors the v dd supply. a 220? reset pulse (t w ) is used internally to keep the device inactive during power on or power off of the v dd supply. see figure 2. temperature monitor card voltage generator and charge pump clock generation control sequencer power-supply supervisor i/o transceiver v dd gnd v dda pgnd cp1 cp2 v up v cc xtal1 xtal2 clkdiv1 clkdiv2 5v/3v cmdvcc rstin cgnd rst clk pres pres i/o aux1 aux2 off i/oin aux1in aux2in DS8024 figure 1. functional diagram v dd alarm (internal signal) power on t w t w power off v th2 + v hys2 v th2 supply dropout figure 2. voltage supervisor behavior
DS8024 smart card interface 8 _______________________________________________________________________________________ the DS8024 card interface remains inactive no matter the levels on the command lines until duration t w after v dd has reached a level higher than v th2 + v hys2 . when v dd falls below v th2 , the DS8024 executes a card deactivation sequence if its card interface is active. clock circuitry the clock signal from the DS8024 to the smart card (clk) is generated from the clock input on xtal1 or from a crystal operating at up to 20mhz connected between pins xtal1 and xtal2. the inputs clkdiv1 and clkdiv2 determine the frequency of the clk sig- nal, which can be f xtal , f xtal/2 , f xtal/4 , or f xtal/8 . table 1 shows the relationship between clkdiv1 and clkdiv2 and the frequency of clk. do not change the state of pins clkdiv1 and clkdiv2 simultaneously; a delay of 10ns minimum between changes is required. the minimum duration of any state of clk is 8 periods of xtal1. the hardware in the DS8024 guarantees that the fre- quency change is synchronous. during a transition of the clock divider, no pulse is shorter than 45% of the smallest period, and the clock pulses before and after the instant of change have the correct width. to achieve a 45% to 55% duty factor on pin clk when no crystal is present, the input signal on xtal1 should have a 48% to 52% duty factor. transition time on xtal1 should be less than 5% of the period. with a crystal, the duty factor on pin clk may be 45% to 55% depending on the circuit layout and on the crys- tal characteristics and frequency. the DS8024 crystal oscillator runs when the device is powered up. if the crystal oscillator is used or the clock pulse on pin xtal1 is permanent, the clock pulse is applied to the card at time t 4 (see figures 7 and 8). if the signal applied to xtal1 is controlled by the host microcontroller, the clock pulse is applied to the card when it is sent by the system microcontroller (after completion of the activation sequence). i/o transceivers the three data lines i/o, aux1, and aux2 are identical. this section describes the characteristics of i/o and i/oin but also applies to aux1, aux1in, aux2, and aux2in. i/o and i/oin are pulled high with an 11k resistor (i/o to v cc and i/oin to v dd ) in the inactive state. the first side of the transceiver to receive a falling edge becomes the master. when the master is decided, the opposite side switches to slave mode, ignoring subse- quent edges until the master releases. after a time delay t d(edge) , an n transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. when the master side asserts a logic 1, a p transistor on the slave side is activated during the time delay t pu and then both sides return to their inactive (pulled up) states. this active pullup provides fast low-to-high tran- sitions. after the duration of t pu , the output voltage depends only on the internal pullup resistor and the load current. current to and from the card i/o lines is limited internally to 15ma. the maximum frequency on these lines is 1mhz. inactive mode the DS8024 powers up with the card interface in the inactive mode. minimal circuitry is active while waiting for the host to initiate a smart card session. all card contacts are inactive (approximately 200 to gnd). pins i/oin, aux1in, and aux2in are in the high- impedance state (11k pullup resistor to v dd ). voltage generators are stopped. xtal oscillator is running (if included in the device). voltage supervisor is active. the internal oscillator is running at its low frequency. activation sequence after power-on and the reset delay, the host microcon- troller can monitor card presence with signals off and cmdvcc , as shown in table 2. table 1. clock frequency selection clkdiv1 clkdiv2 f clk 0 0 f xtal /8 0 1 f xtal /4 1 1 f xtal /2 1 0 f xtal table 2. card presence indication off cmdvcc status high high card present. low high card not present.
DS8024 smart card interface _______________________________________________________________________________________ 9 when a card is inserted into the reader (if pres is active), the host microcontroller can begin an activation sequence (start a card session) by pulling cmdvcc low. the following events form an activation sequence (figure 3): 1) host: cmdvcc is pulled low. 2) DS8024: the internal oscillator changes to high frequency (t 0 ). 3) DS8024: the voltage generator is started (between t 0 and t 1 ). 4) DS8024: v cc rises from 0 to 5v or 3v with a con- trolled slope (t 2 = t 1 + 1.5 t). t is 64 times the internal oscillator period (approximately 25?). 5) DS8024: i/o, aux1, and aux2 are enabled (t 3 = t 1 + 4t). 6) DS8024: the clk signal is applied to the c3 con- tact (t 4 ). 7) DS8024: rst is enabled (t 5 = t 1 + 7t). an alternate sequence allows the application to control when the clock is applied to the card. 1) host: set rstin high. 2) host: set cmdvcc low. 3) host: set rstin low between t 3 and t 5 ; clk will now start. 4) DS8024: rst stays low until t 5 , then rst becomes the copy of rstin. 5) DS8024: rstin has no further effect on clk after t 5 . if the applied clock is not needed, set cmdvcc low with rstin low. in this case, clk starts at t 3 (minimum 200ns after the transition on i/o, see figure 4); after t 5 , rstin can be set high to obtain an answer to request (atr) from an inserted smart card. do not perform acti- vation with rstin held permanently high. active mode when the activation sequence is completed, the DS8024 card interface is in active mode. the host microcontroller and the smart card exchange data on the i/o lines. atr cmdvcc rst rstin clk v cc i/o i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act figure 3. activation sequence using rstin and cmdvcc
DS8024 smart card interface 10 ______________________________________________________________________________________ atr cmdvcc rst rstin clk v cc i/o i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act 200ns figure 4. activation sequence at t 3 rst clk v cc cmdvcc i/o t 10 t de t 12 t 13 t 14 t 15 figure 5. deactivation sequence
DS8024 smart card interface ______________________________________________________________________________________ 11 deactivation sequence when the host microcontroller is done communicating with the smart card, it sets the cmdvcc line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode. the following sequence of events occurs during a deactivation sequence (figure 5): 1) rst goes low (t 10 ). 2) clk is held low (t 12 = t 10 + 0.5 t), where t is 64 times the period of the internal oscillator (approxi- mately 25?). 3) i/o, aux1, and aux2 are pulled low (t 13 = t 10 + t). 4) v cc starts to fall (t 14 = t 10 + 1.5 t). 5) when v cc reaches its inactive state, the deactiva- tion sequence is complete (at t de ). 6) all card contacts become low impedance to gnd; i/oin, aux1in, and aux2in remain at v dd (pulled up through an 11k resistor). 7) the internal oscillator returns to its lower frequency. v cc generator the card voltage (v cc ) generator can supply up to 80ma continuously at 5v or 65ma at 3v. an internal overload detector triggers at approximately 120ma. current samples to the detector are filtered. this allows spurious current pulses (with a duration of a few ?) up to 200ma to be drawn without causing deactivation. the average current must stay below the specified maximum current value. see the applications information section for recommen- dations to help maintain v cc voltage accuracy. fault detection the DS8024 integrates circuitry to monitor the following fault conditions: short-circuit or high current on v cc card removal while the interface is activated ? dd dropping below threshold card voltage generator operating out of the speci- fied values (v dda too low or current consumption too high) overheating there are two different cases for how the DS8024 reacts to fault detection (figure 6): outside a card session ( cmdvcc high). output off is low if a card is not in the card reader and high if a card is in the reader. the v dd supply is monitored? decrease in input voltage generates an internal power-on reset pulse but does not affect the off signal. short-circuit and tempera- ture detection are disabled because the card is not powered up. within a card session ( cmdvcc low). output off goes low when a fault condition is detected, and an emergency deactivation is performed auto- matically (figure 7). when the system controller resets cmdvcc to high, it may sense the off level again after completing the deactivation sequence. this distinguishes between a card extraction and a hardware problem ( off goes high again if a card is present). depending on the con- nector? card-present switch (normally closed or normally open) and the mechanical characteristics of the switch, bouncing can occur on the pres sig- nals at card insertion or withdrawal. the DS8024 has a debounce feature with an 8ms typi- cal duration (figure 6). when a card is inserted, output off goes high after the debounce time delay. when the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on pres and output off goes low. stop mode (low-power mode) the DS8024 (like the tda8024) does not support a low- power stop mode. for applications requiring low-power support, refer to the ds8113. smart card power select the DS8024 supports two smart card v cc voltages: 3v and 5v. the power select is controlled by the 5v/ 3v signal as shown in table 3. v cc is 5v if 5v/ 3v is assert- ed to a logic-high state, and v cc is 3v if 5v/ 3v is pulled to a logic-low state. table 3. v cc select and operation mode 5v/ 3v cmdvcc v cc select (v) card interface status 0 0 3 activated 0 1 3 inactivated 1 0 5 activated 1 1 5 inactivated
DS8024 smart card interface 12 ______________________________________________________________________________________ debounce debounce v cc pres off deactivation caused by cards withdrawal deactivation caused by short circuit cmdvcc figure 6. behavior of pres, off , cmdvcc , and v cc rst clk v cc pres off i/o t 10 t de t 12 t 13 t 14 t 15 figure 7. emergency deactivation sequence (card extraction)
DS8024 smart card interface ______________________________________________________________________________________ 13 DS8024 maxq1103 100nf 100nf +3.3v +3.3v +3.3v 100k 100k 33pf 100nf* 220nf* *place a 100nf capacitor close to DS8024 and place a 220nf capacitor close to card contact. 100nf 33pf clkdiv1 clkdiv2 5v/3v off rstin cmdvcc aux2in aux1in i/oin pres gpio ... ... ... ... gpio isoio0 gpio ... ... ... gpio isoio1 v cc rst clk i/o aux1 aux2 cgnd xtal1 xtal2 v up gnd v dd cp1 cp2 +10 f pgnd v dda 100nf 100nf* 220nf* v dd DS8024 100nf 100nf +3.3v 33pf 100nf 33pf i/oin aux1in aux2in cmdvcc rstin off 5v/3v clkdiv2 clkdiv1 pres cgnd aux2 aux1 i/o clk rst v cc xtal1 xtal2 v up gnd v dd cp1 cp2 +10 f pgnd v dda 100nf v dd figure 8. typical application diagram
DS8024 smart card interface 14 ______________________________________________________________________________________ applications information performance can be affected by the layout of the appli- cation. for example, an additional cross-capacitance of 1pf between card reader contacts c2 (rst) and c3 (clk) or c2 (rst) and c7 (i/o) can cause contact c2 to be polluted with high-frequency noise from c3 (or c7). in this case, include a 100pf capacitor between contacts c2 and cgnd. application recommendations include the following: ensure there is ample ground area around the DS8024 and the connector; place the DS8024 very near to the connector; decouple the v dd and v dda lines separately. these lines are best posi- tioned under the connector. the DS8024 and the host microcontroller must use the same v dd supply. pins clkdiv1, clkdiv2, rstin, pres, aux1in, i/oin, aux2in, 5v/ 3v , cmdvcc , and off are referenced to v dd ; if pin xtal1 is to be driven by an external clock, also reference this pin to v dd . trace c3 (clk) should be placed as far as possi- ble from the other traces. the trace connecting cgnd to c5 (gnd) should be straight (the two capacitors on c1 (vcc) should be connected to this ground trace). avoid ground loops among cgnd, pgnd, and gnd. decouple v dda and v dd separately; if the two supplies are the same in the application, they should be connected in a star on the main trace. connect a 100nf capacitor (esr < 100m ) between v cc and cgnd and place near the DS8024? v cc pin. connect a 100nf or 220nf capacitor (220nf pre- ferred, esr < 100m ) between v cc and cgnd and place near the smart card socket? c1 con- tact. with all these layout precautions, noise should be kept to an acceptable level and jitter on c3 (clk) should be less than 100ps. selector guide note: contact the factory for availability of other variants and package options. + denotes a lead-free/rohs-compliant package. part current voltages supported (v) supports stop mode pin- package DS8024-rjx+ 3.0, 5.0 no 28 tssop DS8024-rrx+ 3.0, 5.0 no 28 so package type package code document no. 28 so (300 mils) 21-0042 28 tssop 56-g2020-001 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
DS8024 smart card interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. emvco approval of the interface module (ifm) contained in this terminal shall mean only that the ifm has been tested in accorda nce and for sufficient conformance with the emv specifications, version 3.1.1, as of the date of testing. emvco approval is not in any way an endorsem ent or warranty regarding the completeness of the approval process or the functionality, quality or performance of any particular product or service. emv co does not warrant any products or services provided by third parties, including, but not limited to, the producer or provider of the ifm and emvco ap proval does not under any circumstances include or imply any product warranties from emvco, including, without limitation, any implied warranties of merc hantability, fitness for pur- pose, or noninfringement, all of which are expressly disclaimed by emvco. all rights and remedies regarding products and servic es which have received emvco approval shall be provided by the party providing such products or services, and not by emvco and emvco accepts no liabil ity whatsoever in connection therewith. revision history revision number revision date description pages changed 0 6/08 initial release. 1 8/08 clarified the v dda specification in the recommended dc operating conditions table. 2

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